In a conventional phase-locked loop (PLL) circuit, a phase detector may provide signals to a charge pump in response to a reference signal and a feedback signal. Output voltages from loop filter nodes of the charge pump are provided to a voltage controlled oscillator (VCO) which increases or decreases the frequency of the feedback signal in response to the output voltages. As a result, the phase between the reference signal and feedback signal can be adjusted.
Typically, it is desirable to maintain a common mode voltage at the loop filter nodes in order to permit a satisfactory voltage swing on the inputs of the VCO. Unfortunately, when the PLL is in lock (i.e., when reference and feedback signals are in phase), conventional PLL charge pumps typically provide simultaneous current flow through both loop filter nodes only for short time periods (for example, 300 psec) which may correspond to a reset time associated with flip flops of the phase detector. In various applications, these short time periods can provide insufficient time for the charge pump to correct the common mode voltage at the loop filter nodes in order to keep the common mode voltage within desired limits.
As a result, the common mode voltage can drift. This drift is highly undesirable as it can saturate the output stage of the charge pump and the input stage of the VCO, thus severely affecting the overall performance of the PLL. Charge pump designs operating at relatively low frequencies, receiving low supply voltages, or providing small output currents suffer most from this problem. Accordingly, there is a need for an improved approach to charge pump circuitry with improved common mode voltage correction.